1. Field of the Invention
The present invention relates to a system-on-chip and a method of testing the same, and more particularly to a system-on-chip capable of being tested using one test pin or without any test pins and a method of testing the same.
2. Description of the Related Art
Generally, system-on-chip size and power consumption may increase as pins are added to the chip. Therefore, it is preferable to reduce or remove one or more test pins that are only used to test devices.
In case of an image chip where pins are only provided to receive a clock signal and a reset signal, there is no spare pin for receiving test signals according to a test vector during a test. Thus, one or more pins are required to test an image chip.
Moreover, new technology needs to be developed to set various test modes without additional test pins because it is complex to set various test modes in a chip with a small number of pins such as the image chip only using a function pin as a test pin.
Since electronic devices such as mobile devices call for minimized sizes, it is desired that chips used in electronic devices be reduced in size. Where chips are decreased in size, it is complicated to properly arrange input/output pins such as data input/output pins and power supply pins on one or two sides. Thus, eliminating test pins is beneficial. Additionally, test items for chips in portable electronic devices have been increased, resulting in more test pins being included.
FIG. 1 shows a pin arrangement of a conventional system-on-chip having test pins disposed at three sides thereof and FIG. 2 shows a pin arrangement of a conventional system-on-chip having test pins disposed at two sides thereof.
A chip in FIG. 1 has a plurality of, for example, four test pins TEST_1 to TEST_4, a RESET pin, a CLK pin, and a plurality of input/output pins IO_1 to IO_7. The input/output pins IO_1 to IO_7 are dedicated to normal modes of operation. A chip in FIG. 2 has a test pin TEST, a reset pin RESET, a clock pin CLK, and a plurality of input/output pins IO_1 to IO_7. A part of the input/output pins IO_1 to IO_7 may be used for test modes of operation. If a chip has fewer input/output pins, it is complicated to perform test modes of operation based on a test system of FIG. 2.